Synopsys Users Group (SNUG)

#ICYMI Synopsys recently introduced Ultra Ethernet and UALink IP solutions that will enable massive #AI clusters to be scaled both out and up. https://bit.ly/3DoEaCN These solutions provide the high-bandwidth, low-latency interconnects needed for next-gen AI and #HPC architectures. Learn more. ⬆️

Rebellions, a pioneering #AI chip company based in South Korea, is poised to lead the next wave of AI acceleration technology. Discover how the Rebellions collaboration with Synopsys is shaping the future of AI in our latest LinkedIn article. Hint: It involves integrating Synopsys’ ZeBu emulation system, Virtualizer, and VCS into their novel AI software and hardware verification methodology.

We're excited to showcase our latest 224G Ethernet multi-vendor interop demo, shared in partnership with MultiLane.🤝 Watch it in action and click here to learn more: https://bit.ly/48RZzQi Thanks Keivan Javadi Khasraghi and Hani Dou for doing a great job at the OIF booth at #ECOC24!

By leveraging #AI-driven optimization from Synopsys Fusion Compiler and DSO.ai, the Synaptics team reduced design turn-around time and improved power consumption. Discover the full insights in our latest LinkedIn article.

Today, Synopsys launched the industry's first Ultra Ethernet and UALink IP solutions designed to connect massive AI accelerator clusters: https://bit.ly/3ZC9Vjk   Fast, scalable connections have become critical, and these solutions have been designed to meet the demands for high-bandwidth and low-latency interconnects.  🔹 Ultra Ethernet IP:  Scale out with up to 1.6 Tbps bandwidth  🔹 UALink IP:  Scale up with up to 200 Gbps throughput per lane    Read more in today’s announcement and learn why industry leaders like AMD, Astera Labs, Juniper Networks, Tenstorrent, and XConn Technologies Holdings Inc. are collaborating with us on this exciting new technology.

The shift from monolithic to multi-die design is inevitable — but that's not to say it's straightforward. Together with Alchip Technologies, a high-performance computing (#HPC) and #AI ASIC company, Synopsys is addressing chiplet-based design challenges to deliver ROI and physical benefits of a multi-die design. Learn more. 👇

Synopsys showcased the world's first multi-vendor CXL 3.1 IP interop demo and shared how real-time silicon-level data can improve digital twin simulations at #SC24: https://bit.ly/3YZlhNR Learn what was presented and how we're advancing software-defined, silicon-optimized data centers in our blog post. 👆

Synopsys recently joined the Ethernet Alliance at the 2024 European Conference on Optical Communication (#ECOC24) to showcase the robustness and interoperability of 800G. https://bit.ly/4fXDeDu Discover new high-speed interconnects and the progression of standards – from paper to field deployment – in our latest blog post.

Working with Teledyne LeCroy, Synopsys delivered the world’s first CXL 3.1 multi-vendor interoperability demonstration at #SC24. Discover how CXL 3.1 increases memory utilization and reduces power consumption. ➡️ https://bit.ly/40Xfo6r

Struggling with the limitations of legacy memory solutions? Discover how MRAM and RRAM are paving the way for innovation in automotive systems, IoT devices, and AI accelerators: https://bit.ly/3ZfHlUL With seamless on-chip integration, low power consumption, and extremely high density, they are a perfect fit for today’s and tomorrow’s computational needs. Click the link above to learn more. ☝️