Circuits and Systems Group of NTUA

✅️ Excited to share that I presented our co-authored paper entitled "A Low-Power Analog Integrated Artificial Neural Networks for Electrical Impedance Tomography Stroke Classification" in the 36th IEEE International Conference on Microelectronics (ICM) ( https://lnkd.in/ex7xNwzr ) which took place in Doha, Qatar between 14th and 17th of December. ✅️ I would like to thank my co-authors Vasileios Alimisis , Andreas Papathanasiou, Savvas Leventikidis and Paul Sotiriadis for their invaluable contribution. 🏁 During the conference, I also had the opportunity to co-chair the "IoT Hardware Intrinsic Attacks", the "Analog and RF Circuit Design Techniques-II" as well as the "Energy Efficient Computing Based on Emerging Technologies" sessions. 🚀 My participation in ICM 2024 was an incredible experience which enriched my own perception in the field of electronics design and gave me the chance to brainstorm with many academic researchers and designers from the industry.

We are pleased to announce that the paper entitled "A Low-Power Analog Vector-Length Calculator Classifier for Fetal Health Classification" received the Best PhD Symposium Paper Award in the Springer 2nd International Conference on Frontiers of Artificial Intelligence, Ethics, and Multidisciplinary Applications; 1st-2nd October 2024, Athens, Greece. https://www.faiema.org/ The Award-Winning paper was co-authored by Konstantinos Cheliotis (Diploma Student, ECE- NTUA and Researcher Archimedes/Athena RC), Vassilis Alimisis (Postdoctoral Researcher, ECE-NTUA and Researcher Archimedes/Athena RC), Andreas Papathanasiou (Graduate, ECE-NTUA), Ourania Ntasiou (Graduate, ECE-NTUA), and Paul P. Sotiriadis (Professor, ECE-NTUA; Lead Researcher, Archimedes/Athena RC; IEEE Fellow). ABSTRACT: This research presents a novel, low-power, fully analog integrated circuit for classifying fetal health data. The circuit leverages a centroid-based approach, employing Vector Length calculations and current comparisons. Notably, it achieves high classification accuracy (93.8%) while consuming only 675nW. This design prioritizes energy efficiency by operating transistors in the sub-threshold region while maintaining robustness. To validate its effectiveness, the proposed circuit is compared against existing software and hardware-based classifiers. Python programming language was used to train the classification model and process the resulting data. The design and simulations were conducted within the Cadence IC Suite environment, utilizing the TSMC 90nm CMOS process technology.

I am thrilled to share that my Ph.D. dissertation, titled "Stochastic Computing Architectures for Information Processing Systems", has been honored with the Iakovos Giourounlian Award for 2023 by the National Technical University of Athens and the School of Electrical and Computer Engineering - NTUA. This award is granted annually to the two best Ph.D. dissertations, recognizing research that demonstrates significant industrial relevance in addition to theoretical contributions. I am deeply honored and grateful to have my work recognized in this way. I would like to sincerely thank Paul Sotiriadis for his supervision as well as the members of the research committee, Athanasios D. Panagopoulos and Kiamal Pekmestzi, for their guidance and support. Special thanks to the ΕΛΙΔΕΚ - Ελληνικό Ίδρυμα Έρευνας και Καινοτομίας (Hellenic foundation for Research & Innovation - HFRI) for financially supporting my Ph.D. dissertation. Link to the Iakovos Giourounlian Award announcement: https://lnkd.in/dZD7ExCr

We are excited to share one of the November 2024 paper highlights "Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification". 📝 Authored by: Vassilis Alimisis; Emmanouil Anastasios Serlis; Andreas Papathanasiou; Nikolaos P. Eleftheriou; Paul Sotiriadis This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. 🔗 Continue reading here: https://loom.ly/zVHimwg #TVLSI #VeryLargeScaleIntegrationSystems #VeryLargeScaleIntegration #PaperHighlight

Two members of our group who presented their work at the Panhellenic Conference On Electronics And Telecommunications (PACET) in Thessaloniki from 28 to 29 March 2024.

Some members of our group who presented their work at the Panhellenic Conference On Electronics And Telecommunications (PACET) in Thessaloniki from 28 to 29 March 2024.

This is the poster that was presented at the Panhellenic Conference On Electronics And Telecommunications (PACET) in Thessaloniki from 28 to 29 March 2024 titled "An Analog Integrated, Low Power Manhattan Dinstance Network with Application to Chronic Kidney Disease Classification" and authored by Vassilis Alimisis, Nikolaos P. Eleftheriou and Paul Peter Sotiriadis.