Elephantech Inc.’s Post

Just Announced! https://lnkd.in/gzKtxgFs Aroma Bit Succeeds in Developing the World's Smallest*1 High-Odor Resolution CMOS Semiconductor-Based Odor Imaging Sensor Chip   Aroma Bit, Inc. (Representative Director & President: Shunichiro Kuroki, Headquarter: Chuo-ku, Tokyo, hereinafter "Aroma Bit"), a company that plans and develops compact odor sensors and innovative services using these sensors, has announced that it has successfully developed a prototype of e-nose type odor imaging sensor using CMOS semiconductors that is the world’s smallest*1, highly-integrated and high odor resolution. Aroma Bit have designed and fabricated a new CMOS semiconductor type odor imaging sensor chip, with a sensor element area of only 1.2 x 1.2 mm, equipped with peripheral driver and A/D converter circuits. A demonstration test of the technology is then conducted to form as many odor-receptor membranes as possible in the sensor element area of this prototype chip. The membrane was deposited using the printing technology of SIJ Technology, which possesses super inkjet technology capable of forming the world's smallest droplets capable of single-micron-level fine dispensing. As a result, Aroma Bit have established a basic technology that enables us to configure 100 odor-receptor membranes within a sensor element area of only 1.2 x 1.2 mm, which translates into the realization of the world's smallest*1 e-Nose type odor sensor, with the world's highest density sensor element array to date. Since this will enable easy sensor integration in a variety of devices, Aroma Bit intends to accelerate market development, for application market requiring low-cost and high-volume. Aroma Bit, Inc.: https://lnkd.in/gV3mcH2R Overview of e-Nose type Odor imaging sensor chip prototype 1. Miniaturization With the 1.2 x 1.2 mm sensor area and 57,600 sensor elements, this transducer is the world's smallest*1 and world’s highest density sensor array for e-Nose type odor sensors. The accompanying peripheral circuitry is also mounted on the chip, making it possible to easily incorporate the transducer into various devices. 2. Improved odor discrimination (odor resolution) performance In this successful prototype, Aroma Bit have demonstrated that it is possible to deposit more than 100 odor-receptor membranes on the above 1.2 x 1.2 mm sensor area, using super inkjet technology with the cooperation of SIJ Technology. By making full use of these technologies, Aroma Bit plans to consider future product lineups with up to 40-50 different odor receptor membranes. Chip Die Size 3.2 x 3.4 mm Sensor Area Size 1.2 x 1.2 mm Sensor Element 240 x 240 Sensor Elements (57,600 Elements) Chip-embedded Circuitry Sensor Driver Circuit AD Converter Circuit Odor Receptor Membrane deposited 100 membranes

Toray has developed a groundbreaking RFID system using a semi-conductive carbon nanotube composite. This printed RFID system communicates via ultrahigh frequency (UHF) and offers advantages like low-cost production, long-distance communication, and efficient inventory management. The innovation addresses the cost and complexity challenges of traditional silicon-based RFID tags, aiming to enhance supply chain operations in retail and logistics. By leveraging carbon nanotubes, the technology enables faster, more efficient data transmission and opens possibilities for broader industrial applications. For more details, you can visit the following link: https://lnkd.in/gAKJGaYt -------------------------------------------------------- Please consult also the Quantum Server Marketplace platform for the outsourcing of computational science R&D projects to external expert consultants through remote collaborations: https://lnkd.in/eRmYbj4x #materials #materialsscience #materialsengineering #computationalchemistry #modelling #chemistry #researchanddevelopment #research #MaterialsSquare #ComputationalChemistry #Tutorial #DFT #simulationsoftware #simulation

As the printing industry evolves, AI is emerging as a powerful tool, helping companies stay competitive and improve efficiency. Our latest insights reveal how companies using AI are outpacing their competition, improving efficiency, and navigating economic challenges. At DPi, we’re committed to staying at the forefront of innovation, integrating advanced technologies that help us and our customers thrive. Curious how AI is reshaping the print world? Read the full article to learn more: https://lnkd.in/gxFJ_P38 #PrintInnovation #AIinPrinting #PrintingTrends #IndustryLeadership #DPiForward

Nice intro to 2.5 and 3 D packaging

It is our pleasure to announce that the 𝗘𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰𝘀 𝗠𝗮𝗻𝘂𝗳𝗮𝗰𝘁𝘂𝗿𝗶𝗻𝗴 & 𝗣𝗮𝗰𝗸𝗮𝗴𝗶𝗻𝗴 𝗦𝘆𝗺𝗽𝗼𝘀𝗶𝘂𝗺 (𝗘𝗠𝗣𝗦) will take place at ESA/ESTEC in Noordwijk, The Netherlands, from 𝟲 𝗢𝗰𝘁 𝘁𝗼 𝟵 𝗢𝗰𝘁 𝟮𝟬𝟮𝟱. The symposium is organised by the European Space Agency’s Materials, Manufacturing and Assembly section and EEE Components Technologies section, in partnership with IPC, the global electronics association. It aims to review the state-of-the-art and new developments in the fields of printed circuit boards, electronic assembly and packaging technologies. Besides space applications, the scope of the event is widened to include other high-rel market segments, such as defence, automotive, medical and data infrastructure, that are at the heart of Europe’s electronics manufacturing industry. Microprocessor chips and other EEE components do not function in isolation. Back-end packaging of chips as well as system level packaging, when assembling EEE parts on PCBs, make up the nerves and veins of the electronic system, connecting its brains – the chips – through signals and power. The packaging technologies provide the backbone and armour, as the sensitive EEE parts need protection from mechanical and thermal stress to operate reliably and in unison within the electronic system. EMPS will be hosting professional development and technology sessions for the following topics, and more: •   Materials & processes for electronics •   Assembly technologies, including lead-free, solderless, press-fit •   Advanced packaging, including heterogeneous integration, System-in Package, Wafer Level Packaging, 3D packaging •   (U)HDI PCBs, organic substrates •   Additive Manufactured Electronics •   Reliability and testing for harsh environments •   Model-based design for excellence •   Smart manufacturing, machine learning and digitalisation •   High power, high speed applications and photonics •   System integration, packaging and performance •   Supply chain resilience, European sovereignty https://emps.port.ac.uk/

The surging interest in artificial intelligence (AI) is driving a significant uptick in the demand for printed circuit boards (PCBs) and related hardware. Manufacturers are facing the challenge of meeting this increased demand while also navigating potential hurdles. Click the link below to learn more! https://lnkd.in/exUXVD5a #AI #artificialintelligence #PCB #circuitboard #components #manufacturing #electronics #electroniccomponents

The Industry Standard Process for Manufacturing Chips The creation of microchips is a complex and intricate process that can take up to 26 weeks to complete. Within these chips, billions of transistors are meticulously packed into an area roughly the size of a fingernail. Here's a breakdown of how these tiny yet powerful devices are manufactured: The process commences with silicon-rich sand, chosen for its semiconductor properties, which lie between those of an insulator and a conductor. Silicon, being abundant and one of the most common elements on Earth, is an ideal material for this purpose. The silicon sand is mixed with carbon and melted in crucibles, resulting in the production of carbon monoxide and achieving 99% pure silicon. Following further refinement, ultra-pure silicon is obtained. Subsequently, a seed crystal is introduced into molten silicon. As the seed crystal is slowly withdrawn, silicon atoms are deposited on its bottom surface. This process yields a large cylindrical boule or single crystal ingot of pure silicon. These boules are then thinly sliced into wafers, typically ranging from 1 to 12 inches in diameter, with state-of-the-art facilities capable of producing wafers as large as 18 inches in diameter. Once the silicon wafers are cut, the production process proceeds under extremely sterile conditions, free from contaminants and dust. The first step in production is deposition. A thin, non-conducting layer of silicon dioxide is grown or deposited onto the wafer's surface, preparing it for lithography by coating it with photosensitive and light-resistant materials. Next, the critical step of exposure takes place. The prepared silicon wafers are introduced into a lithography machine and exposed to UV light containing the chip's blueprint. Areas exposed to light harden, while unexposed areas are etched away by hot gases, leaving behind a three-dimensional microchip. Additionally, the electrical conductivity of different parts of the chip can be modified by doping them with chemicals under heat and pressure. This process can be repeated hundreds of times for the same chip, resulting in the creation of a more complex integrated circuit with each iteration. Finally, the etching process is employed to remove all material except the thin conducting pathways. @tsmc @tiny tapeout @mosis Pipeloluwa Olayiwola

ADVANCED 2.5 AND 3D SEMICONDUCTOR PACKAGING TECHNOLOGY The 2.5D and 3D packaging technologies encompass various packaging techniques. In 2.5D packaging, the choice of interposer material categorizes it into Si-based, Organic-based, and glass-based interposers, as illustrated in the figure below. Meanwhile, in 3D packaging, the evolution of microbump technology aims for smaller pitch dimensions. However, achieving single-digit pitch dimensions today is made possible through the adoption of hybrid bonding technology, a method that directly connects Cu-Cu, signifying a significant advancement in the field. 2.5D semiconductor packaging configuration Silicon (Si) Si Interposer: Widely used in 2.5D packaging for high-performance computing due to its ability to support fine routing features. However, it faces challenges with high material and manufacturing costs, as well as limitations in packaging area. Si Bridge: A more cost-effective alternative gaining traction, strategically using silicon only where necessary. It overcomes the area limitations of Si interposers, making it a promising option for applications that exceed the reticle limit. Organic-Based Packaging: Overview: Utilizes a fan-out molding compound, not an organic substrate, to lower RC delay through a reduced dielectric constant. It offers a more affordable alternative to silicon and is emerging in 2.5D packaging. Challenges: Struggles to match the interconnect feature density achievable with silicon-based packages. Glass-Based Packaging: Overview: Gaining attention due to its beneficial properties, including a tunable Coefficient of Thermal Expansion (CTE), high dimensional stability, and smooth surface. These make it a strong candidate for use as an interposer with capabilities close to silicon. Challenges: The ecosystem is still immature, and large-scale mass production is currently limited, though future growth is anticipated as the technology advances. 3D semiconductor packaging configuration Microbump Technology: Overview: A widely used technology relying on thermal compression bonding (TCB). Challenges: As bump pitches shrink, smaller solder balls lead to increased Intermetallic Compounds (IMCs), reducing conductivity and mechanical strength. Tight gaps risk solder bridging, which can cause chip failure. The higher resistivity of solder and IMCs limits their effectiveness in high-performance applications. Hybrid Bonding: Overview: Combines dielectric material (SiO2) and embedded metal (Cu) to create permanent connections, achieving pitches below 10 micrometers. Advantages: Offers more I/O, better bandwidth, enhanced 3D stacking, improved power efficiency, and reduced parasitics and thermal resistance. Challenges: The technique is complex and costly to manufacture. Image Source - Overview of advanced semiconductor packaging technologies. Courtesy: IDTechEx – “Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications”

What are the 6 key difference between OSAT and Chip fab ? 🚀 Core Function Chip Fab: The primary focus is on the front-end processes, which include creating the actual silicon wafer and fabricating the circuitry on it using photolithography, etching, doping, and deposition. OSAT: OSAT providers handle the back-end processes, such as assembly, packaging, and testing of the semiconductor chips. They take the manufactured silicon wafers from chip fabs, cut them into individual chips, package them, and conduct final testing. 🚀 Type of Work Chip Fab: Involves highly sophisticated front-end fabrication work, including creating the intricate patterns on silicon wafers that form the circuits inside a chip. This requires expensive equipment like lithography machines and cleanroom facilities. OSAT: In contrast, OSAT focuses on assembly and testing, where the wafers are cut into individual dies, connected to external leads, and encapsulated to form a durable and functional package. They also perform extensive reliability and stress testing. 🚀 Facilities and Equipment Chip Fab: Requires extremely high-tech, capital-intensive facilities, including specialized cleanrooms and complex equipment such as extreme ultraviolet (EUV) lithography systems, deposition tools, and ion implanters. OSAT: OSAT facilities are typically less capital-intensive than fabs but still require advanced machinery for dicing, wire bonding, flip-chip bonding, and automated testing. They also need some degree of cleanroom environment for the packaging process. 🚀 Technology Focus Chip Fab: Focuses on semiconductor fabrication technologies like photolithography, CVD and atomic layer etching (ALE). The goal is to make smaller, more powerful, and efficient chips. OSAT: Focuses on assembly and packaging technologies, such as wire bonding, die bonding, flip-chip, and wafer-level packaging, along with electrical and environmental testing. The goal is to create durable, reliable, and compact chip packages that can be integrated into end devices. 🚀 Business Model Chip Fab: The business is focused on producing wafers and making advancements in chip performance and efficiency. OSAT: OSAT providers work in a service-oriented model, primarily supporting fabless companies and IDMs. They focus on packaging and testing, often working on a contractual basis for multiple clients. 🚀 Final Product Chip Fab: Delivers a wafer with chips etched on it, which still needs to be separated, packaged, and tested. OSAT: Provides final, tested, and packaged semiconductor devices ready to be integrated into electronics such as smartphones, computers, or cars. -------------------- P.S: If you like writings like these, we have compiled 100s of such questions in our book- The semiconductor Saga- a book that teaches you everything about semiconductors in simple words. Link in comments.

Thin film electronics is a rapidly evolving technology that has the potential to revolutionize supply chains and shipping as well as other industries. According to a Comprehensive Research Report by Market Research Future (MRFR), the printed electronics market could thrive at a rate of 13.0 percent between 2023 and 2032 and the market size is expected to reach around $12.3 billion by the end of the year 2032. https://okt.to/vyFWQz #technology #supplychainchallenges #visibility #Devices #traceability