Darshan KR’s Post

Last week, I re-read an introduction to the AXI4 Protocol and I learned a lot! I enjoy revisiting specifications because they often help help fill gaps in my initial (and forgotten) understanding. I downloaded an AXI4 introduction from ARM which helped me refresh several concepts: • Atomic accesses • Unaligned transfers • Exclusive accesses • Transaction flows (I had forgotten that the first beat of write data can come before the AW transfer - and is legal) I wish AXI specs also used the time-space diagrams like the CHI specifications—they’re super helpful. By the way, I always forget how the ACE Cache states map to the more familiar MOESI protocol so I thought I’d share it here! How do you remember this? #rtldesign #verilog #riscv #servingTheNextBug #lowpowerdesign #verification #semiconductors #verificationengineer

All in on #Transformer, it is beating all other architectures in end-to-end applications. Like #Etched, #Skymizer is betting on Transformer only accelerator with compiler-centric approach. Skymizer’s first IP product, EdgeThought, is a transformer based on-device LLM inferencing only accelerator.

Mobilize M-Code From The Lab to The Field. 🔹BroadSim MNSA, the real-deal of M-Code simulation, is available today. Now including Increment 2 SDS M-Code, test MGUE performance and security with full control over scenario settings 🔹SecureSync, the flagship for essential timing and synchronization, is ready to ship with M-Code, offering improved resistance to jamming, advanced security features, and more accurate performance. ➡️ Get solutions for rapid deployment: https://lnkd.in/e4S2vf2M #PNT #MCode #Simulation #Timing #RapidDeployment

Watch i-RADAR in action! Intelligent and smart debug for #riscv #formalverification.

Hey there!!! This challenge #21DaysofRTL day20, problem stated as APB System containing the instantiations of Arbiter to FIFO to APB Master to and fro APB Slave. Go through the code to understand the system's whole scenario. Check the git repo from my profile. This creates write responses more often and read responses after the valid and data out process. I will be back with the last challenge of this series. Keep following for more content. #verilog #systemverilog #digitalsystems #digitalelectronics #digitalarchitecture #computers #computing #electronics #digitalsystems #coding #computerarchitecture #communication #switches #routers #chips #muxes #protocols #axi #ahb #apb #interfaces #memory #registers #bridges #computerorganization #fifo #synchronousfifo

In this latest episode of our RISC-V series, we discuss how to make debugging smarter and faster. Discover the next-generation intelligent debug techniques for RISC-V processor verification, designed to enhance both efficiency and accuracy. 🔗 Watch the full episode on our YouTube channel: https://lnkd.in/eaRsyG9w 🔍 Ready to make debugging more intelligent? What challenges are you facing with debugging today? Let us know in the comments below! At Axiomise, we’re here to help you with formal verification to prove bug absence and hunt down corner-case bugs in your ASIC/FPGA designs, RISC-V or otherwise. To learn more, visit our website at www.axiomise.com #RISCV #FormalVerification #ASIC #FPGA #Debugging #Verification #Axiomise #YouTube #Iloveformal #makeformalnormal #bugabsence

Distributed LLM inference over a network? Yea that exists, and teams on the llama.cpp (https://lnkd.in/gpjZF5ic) and LocalAI (https://lnkd.in/gQ5iuDRZ) projects are making it easier and better all the time. This tech could easily lead to large community backed swarms for LLM inference. Think about that... Interested in seeing it in action, then check out some of the lab testing. https://lnkd.in/gy9J5BrN #localai #llm #llama3

𝐁𝐨𝐨𝐬𝐭 𝐒𝐲𝐬𝐭𝐞𝐦𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧 𝐩𝐞𝐫𝐟𝐨𝐫𝐦𝐚𝐧𝐜𝐞 𝐛𝐲 𝟑𝟎𝐗-𝟑𝟎𝟎𝐗? See how by joining our 1-hour technical Lunch and Learn – https://lnkd.in/gUxD-Mm5 - with a step-by-step approach to raising abstraction - still using SystemVerilog and your go-to simulator!

groq lpu are breaking the record on ai llm token processing. I have tried it running some code that uses crewai agentware. it delivers as promised. however, agents need precise answers to converge to a solution, and they need all the precision they can get like chatgpt4.0 for now groq api is free to use, so worth trying for learning to gen ai app development.

UVM TLM Interfaces: These enable the transfer of arbitrary objects among components. Here is an attempt to document the fundamentals of the TLM ports for a better foundation... #systemverilog #uvm #tlm #tlm1