From the course: Learning Verilog for FPGA Development

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Solution: You run the show

Solution: You run the show - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Solution: You run the show

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(bright upbeat music) - [Instructor] So now let me show you my solution. It's pretty straightforward actually. In lines 27 and 28, we have the input and output for the device under test. Speaking of which, in line 29, you can see the declaration of the triple module instance. As I said before, I like to use a naming format for the devices under test. This one is called DUT_triple. Now, as for displaying the results for the requested values, I did it in one line. The monitor task call in line 31 works every time there's a change in the module's input. And finally, I'm assigning all values sequentially with pauses of 10 nanoseconds. Why nanoseconds? Let's look at line 1. Here's the timescale directive showing a unit of one nanosecond and a resolution of one picosecond. Now let me start the simulation. And here we have the timing diagram. Let me resize it so that all of the values are visible. First, I'll maximize…

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