From the course: Learning Verilog for FPGA Development

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Simulation basics

Simulation basics - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Simulation basics

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- [Instructor] Now, it's time to learn how to create your own simulations. So first, here are some quick details about digital circuit simulation in Verilog. The purpose of a simulation is to verify the behavior of your circuit or modules, and it's one of the first automated means of debugging in the development process. A simulation requires a so-called test bench module, which is a regular Verilog module where you get to run the show. Inside a test bench module, the module or device under test, DUT for short, must be instantiated at least once. You must provide a sequence of input signals, and the simulator takes care of the rest, showing you the results in several ways, including a waveform viewer, step-by-step simulation, and a console interface.

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