From the course: Learning Verilog for FPGA Development
Unlock the full course today
Join today to access over 24,000 courses taught by industry experts.
Nonblocking assignments - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
Nonblocking assignments
- [Instructor] Now it's time to learn what non blocking means. Non blocking means that all assignments work concurrently. The term blocking does not refer to the order of events, but rather to the order of evaluation by the compiler in a blocking assignment time is not blocked the compiler is, this project only has one source file, and it doesn't have any test bench modules. In this example, we have a sequential module that takes two inputs, I and clock and outputs a single bit named Oh, we have a temporary registered name temp, and an always block sensitive to the positive edge of the clock line. Now, inside the block, notice that I'm making two blocking assignments in a particular order in lines 26 and 27. First, I'm assigning to temp, the value of I and then I'm assigning the same value to O, so semantically this means that the input goes to the output temp is only there for convenience, it doesn't get synthesized. Let me…
Practice while you learn with exercise files
Download the files the instructor uses to teach the course. Follow along and learn by watching, listening and practicing.
Contents
-
-
-
-
Verilog modules4m 13s
-
(Locked)
Instantiating modules4m 49s
-
(Locked)
Gates and primitives3m 3s
-
(Locked)
Registers and wires1m 46s
-
(Locked)
Range specification4m 30s
-
(Locked)
Numbers and constants4m 53s
-
(Locked)
Always blocks52s
-
(Locked)
The if-else statement2m 2s
-
(Locked)
Case statements2m 24s
-
(Locked)
Boolean algebra expressions56s
-
(Locked)
Continuous assignments2m 23s
-
(Locked)
Blocking assignments3m 20s
-
(Locked)
Nonblocking assignments3m 49s
-
(Locked)
Challenge: From schematic to code2m 16s
-
(Locked)
Solution: From schematic to code4m 31s
-
-
-
-
-