From the course: Learning Verilog for FPGA Development

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Challenge: You run the show

Challenge: You run the show - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Challenge: You run the show

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(upbeat music) - Once again let's see how much you've learned with a challenge, this time you run the show, your task is to write a very Verilog Testbench module, that tests a module named 'triple.' This is the declaration line for that module. It calculates the triple of the number in its input a. The triple is found in its output named result. You must display the results for input values 0, 1, 3, 5, 10, and 15. Please show the results in both the Tcl Console, and the waveform viewer. For your implementation, keep in mind: You may use delays to keep the input values stable for some time. You must use at least one initial statement, with a begin end block. To display the value in the Tcl Console, you must use either the monitor task or the display task. Your simulation must end at some point. So, don't forget the stop task. And please use the provided Vivado simulation project to write and test your code.…

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