From the course: Learning Verilog for FPGA Development

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Always blocks

Always blocks - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Always blocks

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- [Instructor] Verilog supports most of the higher-level statements in programming languages. Up ahead we'll talk about always blocks, if-else statements, case statements, Boolean expressions, and the different types of value assignments available. Always blocks are special constructs that enable procedural blocks of code. Always blocks are evaluated every time some specified condition is met. The syntax for always blocks is simple. Just type always at, followed by a sensitivity list. Registers or signals present in this comma-separated list will be monitored for changes. If any of the variables change, the procedural block is evaluated. Now let's see some examples of procedural block constructs.

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