From the course: Learning Verilog for FPGA Development

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A simple simulation

A simple simulation - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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A simple simulation

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- [Instructor] Let me show you two simulations with the multiplexer and demultiplexer modules we saw earlier. Here's what we'll do in the Multiplexer Test Bench. I'll enter two signals with different frequencies in its inputs. Input zero will have a lower frequency and input one will have a higher frequency. When a zero enters the selection line, the lower frequency signal will appear in the output. And when a one enters the selection line, the higher frequency signal will be at the output. Now, for the Demultiplexer Test Bench, I'll feed an oscillating signal to its input and that signal will go to the output in its selection lines with the rest in a constant zero. So this is how it will behave for the selection input at zero, one, two and three. So here's the project for this simulation. The source files for the multiplexer and the demultiplexer are already included in this project but we'll concentrate on the test…

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