CELERO COMMUNICATIONS INC

A world-class team, strong leadership, a clear vision. 💪🚀

🎉 We are pleased to announce that Leandro Passetti has joined the Celero Communications Inc. team! 🎉 Leandro comes on board as a Principal Analog Design Engineer, bringing a wealth of experience and expertise in analog circuit design. We are thrilled to have him on our team and look forward to the innovative solutions he will contribute to our projects. Welcome, Leandro! Your expertise and experience will be a significant addition to our ongoing success and growth. 🚀 #WelcomeToTheTeam #CeleroCommunications #NewTeamMember #Innovation

🎉 We are excited to announce that Paul Romero has joined the Celero Communications Inc. team! 🎉 Paul joins us as a Senior Engineer - DSP Systems, bringing extensive knowledge and expertise in digital signal processing. We are eager to see the innovative contributions he will make to our projects. Welcome, Paul! Your skills and experience will be a tremendous asset to our ongoing success and development. 🚀 #WelcomeToTheTeam #CeleroCommunications #NewTeamMember #Innovation

We are looking for Physical Design Engineer As a Physical Design Engineer, you'll play a pivotal role in implementing ASIC’s transceiver on TSMC’s cutting-edge process nodes. Responsibilities: Lead physical implementation and tapeout of ASIC, covering block/SOC level floorplan, low power structures, power ground networks, placement, clock tree synthesis, routing, and design optimization. Conduct design signoff verification including RC extraction, STA, IREM, DRC, LVS, ERC, VCLP. Ensure timing, physical, and power/signal integrity closure based on signoff verification results. Develop and evaluate methodologies and flows to achieve PPA targets (power, performance, and area). Create CAD tools to support design flow and quality monitoring dashboards using TCLK/TK, CSH, Python. Key Qualifications: Strong grasp of digital circuit concepts. Knowledgeable in physical design implementation flow, auto placement and routing, static timing analysis, layout design, physical verification, IREM signoff, and CAD development. Familiarity with CAD tools for layout, simulation, and verification. Proficient in scripting languages such as TCL, Python, and CSH. Preferred Qualifications: Master’s Degree or above in Electrical Engineering or Computer Science from a top university, with VLSI-related coursework and projects preferred. Excellent communication and problem-solving skills. Proactive, collaborative, self-motivated, adaptable, and flexible. Hands-on experience with major EDA Tools.

We are looking for ASIC Design Engineer As an ASIC Design Engineer, you'll define chip architecture, block/function specifications, and driving design, simulation, and verification of digital functions on Mixed Signal ASICs. Responsibilities: - Collaborate with system and architecture teams to grasp top-level requirements and translate them into detailed specifications. - Implement functions in Verilog RTL according to specifications. - Conduct thorough unit level testing on RTL functions. - Support design integration activities such as Lint, CDC, Synthesis & ECO. - Liaise with Physical Design Team to resolve STA, physical, power, and logical issues. Key Qualifications: - Demonstrated expertise in digital design, especially RTL design. - Proficient in digital design flow: RTL simulation, logic synthesis, timing closure, STA, and equivalence checking. - Proficiency in scripting languages like Perl/Python, Tcl, and shell scripts for flow automation. - Experience in Low Power design preferred. - Strong familiarity with industry-standard RTL Design & Synthesis tools, Extraction, and STA methodology. - Knowledgeable about best practices in digital logic implementation. - Understanding of Design Verification principles, adept at writing self-checking test suites. Preferred Qualifications: - Master’s or Doctorate in Computer Engineering/Electrical Engineering. 2+ years of hands-on experience in RTL development, covering functional and structural RTL design, design partitioning, simulation, regression, and collaboration with DV team. Familiarity with latest RTL languages and tools, including linting, CDC, etc.

We are looking for SYSTEM DESIGN ENGINEER Key Responsibilities  - Design, model, and analyse communication systems.  - Develop, document, and maintain software for system-level modelling using tools like MATLAB, Python, and/or C++.  - Collaborate with system architects to create and define block-level and system-level specifications.  - Work closely with other engineering teams (analog, digital, and verification) to support the design, modelling, and verification process.  - Assist with post-silicon lab bring-up, debugging, characterization, and productization.  - Generate various reports including progress, analysis, design, modelling, and verification reports.    Skills  - Strong knowledge of communications, signal processing, algorithms, and modelling techniques.  - Proven ability to implement signal-processing algorithms.  - Understanding of digital communication link components and factors affecting link performance (e.g., signalling and modulation schemes).  - Proficiency in at least one of the following programming languages: C++, MATLAB, or Python.  - Familiarity with the git version-control system and basic software engineering principles (unit-testing, profiling, etc.).  - Excellent communication and presentation skills.    Experience  - Over 2 years of experience in the development and modelling of communication, electronic, or computational systems.  - Proficient in system-level modelling and simulation of digital communication systems.  - Expert-level knowledge and practical experience with common modelling and simulation tools such as MATLAB, Python, and C++. 

🎉 We are thrilled to announce that José Francisco Torres Alberto has joined the Celero Communications Inc. team! 🎉 José comes on board as a Senior Engineer - DSP Systems, bringing a wealth of knowledge and expertise in digital signal processing. We eagerly anticipate the innovative contributions he will bring to our projects. Welcome, José! Your skills and experience will be an invaluable addition to our ongoing success and development. 🚀 #WelcomeToTheTeam #CeleroCommunications #NewTeamMember #Innovation

🎉 We are excited to welcome Miguel Perez andrade to the Celero Communications Inc. family! 🎉 Miguel joins us as a Senior Engineer, bringing his extensive experience and skills. We look forward to seeing the innovative solutions he will contribute to our projects. Welcome aboard, Miguel! Your expertise will be a vital asset to our continued growth and success. 🚀 #WelcomeToTheTeam #CeleroCommunications #NewTeamMember #Innovation

🎉 We are thrilled to welcome Facundo Sposetti to Celero Communications Inc.! 🎉 Facundo joins our team as Principal Digital Design Engineer, and we are excited to have his talent and expertise as we continue to innovate and achieve new milestones. Welcome, Facundo! We are confident that your contributions will be key to our ongoing success. 🚀 #Welcome #CeleroCommunications #NewTalent #Innovation